1. Field of the Invention
The invention relates generally to a double data rate (DDR) synchronous random access memory (SDRAM) interface and, more particularly, to a single common symmetrical memory read data path used for DDR memory controller designs supporting both N-bit and N/2-bit external memory data path widths interfacing to 2N width internal buses.
2. Description of the Related Art
In a DDR SDRAM, data is stored in memory at the address corresponding to the data, and the address is aligned to the width of the memory interface. In N-bit mode, data is stored at addresses that reside on N-bit boundaries, with byte selects used to mask and/or enable the individual bytes. Likewise, in (N/2)-bit mode, data is typically stored at addresses that reside on (N/2)-bit boundaries, with byte selects used to mask and/or enable the individual bytes.
For example, in 64-bit mode, data is stored at addresses that reside on 64-bit (8-byte) boundaries, with byte selects used to mask/enable the individual bytes within an 8 byte Doubleword (DW). In other words, DWs are stored on 8-byte boundaries with DW0 stored at address 0, DW1 stored at address 8, etc. Likewise, in 32-bit mode, data is typically stored at addresses that reside on 32-bit (4-byte) boundaries, with byte selects used to mask and/or enable the individual bytes within a 4-byte Word (W). In other words, Words are stored on 4-byte boundaries with W0 stored at address 0, W1 stored at address 4, W2 stored at address 8, W3 stored at address C, etc.
Typically, storing data in (N/2)-bit mode requires additional logic and multiplexing that increases the overall path delays along the DDR read data critical path. Additionally, more complex dynamic multiplexer control (DC) logic is required to enable the capture and steering of the read data. The end result of this is increased delays, increased logic power within the read data path, asymmetrical fan-out that affects both (N/2)-bit and N-bit mode timing, increased physical design complexity and time, and more complex static timing analysis assertion and timing runs.
Therefore, there is a need for a single common symmetrical DDR read data path that can be used for both N-bit and (N/2)-bit memory interfaces.
The present invention provides a read data path structure that can be used for N-bit and (N/2)-bit memory interfaces to a double data rate (DDR) synchronous random access memory (SDRAM). The read data path structure comprises a first flip-flop (FF) receiving lower (N/2)-bit data, a second FF having its input connected to the output of the first FF, and a third FF having its input connected to the output of the second FF. The read data path structure further comprises a first multiplexer having three inputs connected to the output of the first FF, the output of the second FF, and the output of the third FF, a fourth FF having its input connected to the output of the first multiplexer, and a fifth FF receiving upper (N/2)-bit data.
Additionally, the read data path structure comprises a sixth FF having its input connected to the output of the fifth FF, a seventh FF having its input connected to the output of the sixth FF, and a second multiplexer having four inputs connected to the output of the fourth FF, the output of the fifth FF, the output of the sixth FF, and the output of the seventh FF.
Also, the read data path structure comprises an eighth FF having its input connected to the output of the second multiplexer.